Metallization structures for semiconductor device interconnects

ABSTRACT

The present invention provides a metallization structure for semiconductor device interconnects such as a conductive line, including a substrate with a substantially planar upper surface, foundation metal layer disposed on a portion of the substrate upper surface, primary conducting metal layer overlying the foundation metal layer, and metal spacer on the sidewalls of the primary conducting metal layer and the foundation metal layer. The present invention also provides a metallization structure including a substrate with a foundation metal layer disposed thereon, a dielectric layer with an aperture therethrough being disposed on the substrate, where the bottom of the aperture exposes the foundation metal layer of the substrate, and a metal spacer on the sidewall of the aperture and a line or plug of a primary conducting metal fill the remaining portion of the aperture. The present invention also includes methods for making the metallization structures.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 10/112,928,filed Mar. 29, 2002, pending, which is a divisional of application Ser.No. 09/829,161, filed Apr. 9, 2001, pending, which is a divisional ofapplication Ser. No. 09/388,031, filed Sep. 1, 1999, pending.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to the field of semiconductor devicedesign and fabrication. Specifically, the invention relates to methodsfor manufacturing metallization structures in integrated circuit devicesand the resulting structures.

2. State of the Art

Integrated circuits (ICs) contain numerous individual devices, such astransistors and capacitors, that are interconnected by an intricatenetwork of horizontal and vertical conductive lines commonly termed“interconnects.” Exemplary interconnect structures are disclosed in U.S.Pat. Nos. 5,545,590, 5,529,954, 5,300,813, 4,988,423, and 5,356,659,each of which patents is hereby incorporated herein by reference.

Aluminum interconnect structures are decreasing in size and pitch(spacing), as the industry trend continues toward, and includes,submicron features and pitches. The resultant reduction in structuresizes leads to numerous reliability concerns, including electromigrationand stress voiding of the interconnect structures.

Stress notches (also known as stress voids) on the surface of conductiveinterconnect structures are of concern because the voids or notchesdegrade reliability and device performance. Stress notches, when formedin a conductive line, may render the line substantially discontinuousand unable to effectively transmit a signal. Stress notches at a grainboundary are extremely detrimental, as they may propagate along theboundary and sever the conductive line completely.

Stress notches are also undesirable because they can alter theresistivity of a conductive line and change the speed at which signalsare transmitted. Resistivity changes from stress notching are especiallyimportant as line dimensions shrink, because notching in a submicronconductive line alters resistivity more than notching in a larger linewith its consequently greater cross-sectional area. Thus, the ever morestringent pitch sizing and higher aspect ratios (height to width of thestructure or feature) sought by practitioners in the art have imitatedconsiderable stress voiding concerns.

It is believed that stress notching results from both structural andthermal stresses between conductive lines and adjacent insulating andpassivation layers. Kordic et al., Size and Volume Distributions ofThermally Induced Stress Voids in AlCu Metallization, Appl. Phys. Lett.,Vol. 68, No. 8, 19 Feb. 1996, pp. 1060-1062, incorporated herein byreference, describes how stress voids begin at the edge of a conductiveline where the density of the grain boundaries is largest. Asillustrated in FIG. 12 herein, stress notches form at the exteriorsurfaces and surface intersections of the conductive lines in order torelieve areas of high stress concentration. The notches may thenpropagate into, and across, the interior of the conductive line untilthe line becomes disrupted, cracked, and/or discontinuous.

Aluminum (Al) and Al alloy (such as Al/Cu) lines are especiallysusceptible to stress notching because of both the thermal expansionmismatch between Al and adjacent layers and the relatively low meltingpoint of Al. As the temperature changes, stresses are induced in Al orAl alloy lines because aluminum's coefficient of thermal expansion (CTE)differs from the CTE of the materials comprising the adjacent layers. Torelieve these stresses, Al atoms migrate and form stress notches.Further, because Al has a low melting point, Al atoms migrate easily atlow temperatures and aggravate a tendency toward stress notch formation.

Several methods have been proposed to reduce stress notching. Oneproposed method uses a material less susceptible to stress notching,such as copper (Cu) or tungsten (W), in the conductive line. Using Cu inconductive lines, however, has in the past resulted in several problems.First, copper is difficult to etch. Second, adhesion between copper andadjacent insulating layers is poor and thus poses reliability concerns.Third, adding Cu to Al lines may reduce stress notching, but beyond acertain Cu concentration, device performance may begin to degrade.Fourth, as conductive line geometries shrink, adding Cu to Al linesseems less effective in reducing stress notching. Finally, even using Cuinterconnects in the manner employed in the prior art can still lead tonotching effects, especially at 0.1 μm geometries and below since, atsuch dimensions, line widths have become so small that any imperfectioncan cause openings. Using W in Al conducting lines is also undesirable—Whas a high resistivity and, therefore, reduces signal speed.

Another proposed method to reduce stress notching modifies how thelayers adjacent conductive lines (e.g., insulating and passivationlayers) are formed. This method has focused, without notable success, onthe rate, temperature, and/or pressure at which the adjacent layers aredeposited, as well as the chemical composition of such layers.

Yet another proposed method to reduce stress notching comprises forminga cap on the conductive lines. Such caps can be formed from TiN, W, orTi—W compounds. These materials have higher melting points than Al and,therefore, have a higher resistance to stress notching. A disadvantagein using such caps, however, is that additional process steps, such asmasking steps, are required.

U.S. Pat. No. 5,317,185, incorporated herein by reference, describesstill another proposed method for reducing stress notching. This patentdiscloses an IC device having a plurality of conductive lines where theoutermost conductive line is a stress-reducing line. Thisstress-reducing line is a nonactive structure which reduces stressconcentrations in the inner conductive lines.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to a metallization structure forsemiconductor device interconnects comprising a substrate having asubstantially planar upper surface, a metal layer disposed on a portionof the substrate upper surface, a conducting layer overlying the metallayer, and metal spacers flanking the sidewalls of the conducting layerand the underlying metal layer. The metal layer and metal spacers do notencapsulate the conducting layer. The substrate upper surface ispreferably a dielectric layer. The conducting layer preferably comprisesaluminum or an aluminum-copper alloy, but may also comprise copper. Whenthe conducting layer comprises Al, the metal layer and metal spacerpreferably comprise titanium, such as Ti or TiN. An optional dielectriclayer, preferably silicon oxide, may be disposed on the conductinglayer. When the optional dielectric layer is present, the metal spacerextends along the sidewall of the dielectric layer.

The present invention also relates to a metallization structurecomprising a substrate having a metal layer disposed thereon, adielectric layer having an aperture therethrough disposed on thesubstrate so the bottom of the aperture exposes the upper surface of themetal layer, at least one metal spacer on the sidewall of the aperture,and a conducting layer filling the remaining portion of the aperture.The metal layer and metal spacer preferably comprise titanium, such asTi or TiN. At least one upper metal layer may be disposed on theconducting layer.

The present invention further relates to a method for making ametallization structure by forming a substantially planar firstdielectric layer on a substrate, forming a metal layer over the firstdielectric layer, forming a conducting layer over the metal layer,forming a second dielectric layer over the conducting layer, removing aportion of the second dielectric layer, conducting layer, and metallayer to form a multi-layer structure, and forming metal spacers on thesidewalls of the multi-layer structure. The process optionally removesboth the second dielectric layer portion of the multi-layer structureand the laterally adjacent portions of the metal spacers.

The present invention additionally relates to a method for making ametallization structure by forming a substrate comprising a metal layerdisposed thereon, forming a dielectric layer comprising an aperture onthe substrate so the bottom of the aperture exposes the upper surface ofthe metal layer, forming a metal spacer on the sidewall (in the case ofa via) or sidewalls (in the case of a trench) of the aperture, andforming a conducting layer in the remaining portion of the aperture. Atleast one upper metal layer may optionally be formed on the conductinglayer.

The present invention also relates to a method for making ametallization structure by forming a substrate comprising a metal layeron the surface thereof, forming on the substrate a dielectric layercomprising an aperture so the bottom of the aperture exposes the surfaceof the metal layer, forming a conducting layer in the aperture, formingan upper metal layer overlying the dielectric layer and the aperture,removing the portions of the upper metal layer overlying the dielectriclayer, removing the dielectric layer, removing the portions of the metallayer not underlying the aperture to form a multi-layer metal structure,and forming a metal spacer on the sidewall or sidewalls of themulti-layer metal structure.

The present invention provides several advantages when compared to theprior art. One advantage is that thermally induced stress voids arereduced because the metal layer and metal spacer comprise materialsexhibiting good thermal-voiding avoidance characteristics. Anotheradvantage is that the size of conductive lines can be shrunk further incomparison to dimensions achievable by conventional processes, sinceonly one additional deposition and etch step, without an additionalmasking step, is needed to form the metallization structure. Shrinkingof conductive lines is necessary as device geometries decrease to lessthan 0.1 μm. At these small geometries, even small notches cansignificantly decrease conductivity.

The invention also specifically includes semiconductor devices includingthe inventive metallization structures.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The present invention, in part, is illustrated by the accompanyingdrawings in which:

FIGS. 1, 2, 3 a, and 3 b illustrate cross-sectional views of one processof forming a metallization structure, and the structure formed thereby,according to the invention;

FIGS. 4, 5, 6, 7 a, and 7 b illustrate cross-sectional views of anotherprocess of forming a metallization structure, and the structure formedthereby, according to the invention;

FIGS. 8 and 9 illustrate cross-sectional views of yet another process offorming a metallization structure, and the structure formed thereby,according to the invention;

FIGS. 10 and 11 illustrate cross-sectional views of still anotherprocess of forming a metallization structure, and the structure formedthereby, according to the invention; and

FIG. 12 illustrates a partial cross-sectional, perspective view of aconventional, prior art metallization structure exhibiting stress voidsor notches.

DETAILED DESCRIPTION OF THE INVENTION

Generally, the present invention relates to a metallization structurefor interconnects and semiconductor devices including same.Specifically, the present invention reduces stress voiding, especiallythermally induced stress voiding, in conducting lines. The metallizationstructures described below exemplify the present invention withoutreference to a specific device because the inventive process andstructure can be modified by one of ordinary skill in the art for anydesired device.

The following description provides specific details, such as materialthicknesses and types, in order to provide a thorough description of thepresent invention. The skilled artisan, however, would understand thatthe present invention may be practiced without employing these specificdetails. Indeed, the present invention can be practiced in conjunctionwith conventional fabrication techniques employed in the industry.

The process steps described below do not form a complete process flowfor manufacturing IC devices. Further, the metallization structuresdescribed below do not form a complete IC device. Only the process stepsand structures necessary to understand the present invention aredescribed below.

One embodiment of a process and resulting metallization structure of thepresent invention is illustrated in FIGS. 1, 2, 3 a, and 3 b. Thisembodiment may be characterized as a predominantly “subtractive”process, in comparison to the second embodiment discussed hereinafter,in that portions of superimposed material layers are removed to definethe interconnect structure features, such as lines. As shown in FIG. 1,a portion of semiconductor device 2 includes substrate 4 with overlyingfirst dielectric layer 6. Substrate 4 may be any surface suitable forintegrated circuit device formation, such as a silicon or othersemiconductor wafer or other substrate, and may be doped and/or includean epitaxial layer. Substrate 4 may also be an intermediate layer in asemiconductor device, such as a metal contact layer or an interleveldielectric layer. Preferably, substrate 4 is a silicon wafer or bulksilicon region, such as a silicon-on-insulator (SOI) orsilicon-on-sapphire (SOS) structure.

First dielectric layer 6 may comprise any dielectric material used in ICdevice fabrication. Examples of such dielectric materials includesilicon oxide, silicon nitride, silicon oxynitride, silicon oxidecontaining dopants such as boron (B) or phosphorus (P), organicdielectrics, or a layered dielectric film of these materials.Preferably, first dielectric layer 6 is silicon oxide orborophosphosilicate glass (BPSG). First dielectric layer 6 may be formedby any process yielding the desired physical and chemicalcharacteristics, such as thermal oxidation, thermal nitridation, orvapor deposition.

Overlying first dielectric layer 6 is metal layer 8. One or moreindividual metal layers may be used as metal layer 8. For example, iftwo superimposed metal layers are employed (represented by the dashedline in metal layer 8), an adhesion-promoting metal layer can be afirst, lower portion of metal layer 8 on first dielectric layer 6 and astress-reducing layer can be a second, upper portion of metal layer 8.Other metal layers might be included for other functions, such as alayer for reducing electromigration. Preferably, a single metal layer isused as metal layer 8, especially when the single layer can reduceelectromigration, function as an adhesion-promoting layer, and functionas a stress-reducing layer. If two metal layers are employed, the first,upper metal layer may, for example, comprise tantalum, titanium,tungsten, TaN, or TiN and the second, lower metal layer overlying firstdielectric layer 6 may, for example, comprise TiN, TiW, WN, or TaN.

Metal layer 8 includes not only metals, but their alloys and compounds(e.g., nitrides and silicides). For example, a metal layer containingtitanium might also contain nitrogen or silicon, such as titaniumnitride or titanium silicide. Any metal, metal alloy, or metal compoundcan be employed in metal layer 8, provided it exhibits thecharacteristics described above, either alone or when combined withother metal layers. Examples of metals that can be employed in metallayer 8 include cobalt (Co), Ti, W, Ta, molybdenum (Mo), and alloys andcompounds thereof, such as TiW or TiN. Preferably, metal layer 8comprises titanium. Titanium is a good adhesion layer and serves as astress-reducing layer since Ti exhibits good thermal voiding resistancecharacteristics.

Metal layer 8 is deposited or otherwise formed by any process used in ICdevice fabrication. For example, metal layer 8 may be deposited bychemical vapor deposition (CVD) or physical vapor deposition (PVD)techniques, depending on the characteristics required of the layer. Asused herein, the term “CVD techniques” encompasses, without limitation,plasma-enhanced CVD, or PECVD. Preferably, when metal layer 8 is Ti,this layer is formed by sputtering (a form of PVD) a film of Ti. Ifmetal layer 8 is a metal nitride, it may be formed, for example, bydepositing the metal in a nitrogen-containing atmosphere or bydepositing the metal and annealing in a nitrogen-containing atmosphere.If metal layer 8 is a metal silicide, it may be formed, for example, byfirst depositing either the metal layer or a silicon layer, thendepositing the other, and heating to react the two layers and form thesilicide. If metal layer 8 is a metal alloy, it may be formed by anyprocess suitable for depositing the metal alloy. For example, eithersputtering or CVD techniques can be employed.

Conducting layer 10 is then formed over metal layer 8. Conducting layer10 may comprise any conducting material used in IC device fabrication.Preferably, conducting layer 10 comprises a conducting metal, such asAl, optionally containing other elements such as Si, W, Ti, and/or Cu.More preferably, conducting layer 10 is an aluminum-copper alloy.Conducting layer 10 may also be formed of Cu. Conducting layer 10 may beformed by any method used in IC device fabrication such as CVD or PVDtechniques. Preferably, conducting layer 10 is deposited by a PVD methodsuch as sputtering, as known in the art. Second dielectric layer 12 isnext deposited or otherwise formed on top of conducting layer 10. Seconddielectric layer 12 comprises any dielectric material used in IC devicefabrication, including those listed above. Preferably, second dielectriclayer 12 comprises a material that serves as an etch stop, as explainedbelow. More preferably, second dielectric layer 12 comprisesfluorine-doped silicon oxide or other low dielectric constant material.Second dielectric layer 12 may be formed by any suitable process givingthe desired physical and chemical characteristics, such as CVD, PECVD(plasma enhanced chemical vapor deposition), spin-on methods, orotherwise, depending upon the dielectric material selected. For use ofthe preferred fluorine-doped silicon oxide, the preferred depositionmethod is PECVD.

As shown in FIG. 2, portions of second dielectric layer 12, conductinglayer 10, and metal layer 8 have been removed, forming multi-layerstructure 13. The portions of layers 8, 10 and 12 are removed by any ICdevice fabrication process, such as a photolithographic patterning anddry etching process. The resulting multi-layer structure forms the basisfor an interconnect structure according to the present invention. Ofcourse, the patterning and etch process would normally be performed todefine a large number of interconnect structures, such as conductivelines 100 (see FIGS. 3 a and 3 b) extending across substrate 4.

As also shown in FIG. 2, second metal layer 14 (also termed a metalspacer layer) is then deposited on first dielectric layer 6 and overmulti-layer structure 13. In similar fashion to the structure of metallayer 8, one or more individual metal layers, illustrated by the dashedline within second metal layer 14, may be used as second metal layer 14.Preferably, a single metal layer is used as second metal layer 14 forthe same reasons as those set forth for metal layer 8.

Like metal layer 8, second metal layer 14 includes not only metals buttheir alloys and compounds (e.g., nitrides and silicides). Preferably,when conducting layer 10 comprises aluminum, second metal layer 14comprises Ti. If conducting layer 10 comprises Cu, second metal layer 14preferably comprises TiW. More preferably, second metal layer 14comprises the same metal as metal layer 8. Second metal layer 14 may bedeposited or otherwise formed by a process similar to the process usedto form metal layer 8. Preferably, second metal layer 14 is formed by aconformal deposition process, such as CVD.

Next, as illustrated in FIG. 3 a, second metal layer 14 is spacer etchedto remove portions of the second metal layer 14 on first dielectriclayer 6 and on second dielectric layer 12, thereby leaving metal spacers16 on the multi-layer structure 13. A spacer etch is a directionalsputtering etch which removes second metal layer 14 so that metalspacers 16 remain on the sidewalls of multi-layer structure 13. Thespacer etch uses the first and second dielectric layers as an etch stop.

If desired, second dielectric layer 12 can then be removed. Seconddielectric layer 12 can be removed by any process which removes thesecond dielectric layer without removing first dielectric layer 6. Ifthe first and second dielectric layers comprise different materials(e.g., when second dielectric layer 12 is silicon oxide and the firstdielectric layer 6 is BPSG), any process which selectively etches thesecond dielectric layer 12 can be employed. The etch process would alsoremove the portions of metal spacers 16 laterally adjacent dielectriclayer 12, thus resulting in the metallization structure illustrated inFIG. 3 b. When the first and second dielectric layers 6, 12 are similaror have similar etch rates (e.g., when both are silicon oxide orfluorine-doped), a facet etch process can be used. As shown in brokenlines in FIG. 3 b, when the first and second dielectric layers 6 and 12exhibit similar etch rates, the thickness of layer 6 will be reduced bysubstantially the thickness of removed layer 12.

The metallization structures illustrated in FIGS. 3 a and 3 b reducethermally induced stress voids in conductive lines 100. Metal layer 8and metal spacers 16 serve as a protective coating at the respectivelower and lateral surfaces of conductive lines 100 and at intersectionsthereof, thereby reducing the incidence of stress voids by preventingthem from starting at these surfaces and intersections thereof onconductive line 100. Metal layer 8 and metal spacers 16 also increasereliability of conductive line 100 without reducing its resistance.

The metallization structures of FIGS. 3 a and 3 b can then be processedas desired to complete the IC device. For example, an interleveldielectric layer could be deposited thereover, contact or via holescould be cut in the interlevel dielectric, a patterned metal layer couldbe formed to achieve a desired electrical interconnection pattern, and aprotective dielectric overcoat deposited and patterned to expose desiredbond pads.

Another embodiment of a process and resulting metallization structuresof the present invention is represented in FIGS. 4 through 11. Thisembodiment may be characterized as more of an “additive” method orprocess than that described with respect to FIGS. 1 through 3 b, in thatmetallization structures for interconnects are formed by deposition inapertures, such as vias or trenches. As such, it should be noted thatcusping of material deposited to line the sidewall or sidewalls of anaperture may be of concern if the method of deposition is notsufficiently anisotropic or, in some instances, the aperture exhibits avery high aspect ratio. In FIG. 4, metal layer 52 has been deposited orotherwise formed over substrate 50. Any of the substrates employable assubstrate 4 above can be used as substrate 50. Preferably, substrate 50is a silicon wafer or bulk silicon region, such as an SOI or SOSstructure. Such substrate 50 can have active and passive devices andother electrical circuitry fabricated on it, these circuit structuresbeing interconnected by the metallization structures of the presentinvention. Therefore, a direct electrical path may exist between thedevices and circuitry of the substrate 50 (or 4), the devices andcircuitry being omitted herein for simplicity.

Metal layer 52 may comprise a discrete conductive member, such as awire, a stud, or a contact. Preferably, metal layer 52 is substantiallysimilar to metal layer 8 described above and may be of any of the samemetals, alloys or compounds. If desired, a dielectric layer 51 can beformed on substrate 50 and beneath metal layer 52. Dielectric layer 51is substantially similar to first dielectric layer 6 described above.

As illustrated in FIG. 4, dielectric layer 54 is then deposited orotherwise formed on metal layer 52. Dielectric layer 54 may be anydielectric or insulating material used in IC device fabrication, such asthose listed above for second dielectric layer 12. Preferably,dielectric layer 54 is silicon oxide or spin-on glass (SOG). Dielectriclayer 54 may be formed by any IC device fabrication process giving thedesired physical and chemical characteristics.

An aperture 56 such as a via or trench is then formed in dielectriclayer 54 by removing a portion of dielectric layer 54 to exposeunderlying metal layer 52. Aperture 56 may be formed by any IC devicemanufacturing method, such as a photolithographic patterning and etchingprocess.

As shown in FIG. 5, metal collar 60 is formed on the sidewalls ofaperture 56, using a spacer etch as known in the art. It will beunderstood that the term “collar” encompasses a co-parallel spacerstructure 60 if aperture 56 is a trench extending over substrate 50.Similar to second metal layer 14, collar 60 may contain one or moremetal layers with a single metal layer preferably used. Also in similarfashion to second metal layer 14, collar 60 may include not only metals,but their alloys and compounds. Like second metal layer 14, any metalcan be employed in collar 60, provided it exhibits the desiredcharacteristics, either alone or when combined with other metal layers,and the metals applicable to metal layer 14 are equally applicable tocollar 60. Preferably, collar 60 comprises the same metal as metal layer52. More preferably, when metal layer 52 comprises Al, collar 60comprises Ti.

Collar 60 is formed by an IC device fabrication process which does notdegrade metal layer 52, yet forms a collar or spacer-like structure 60on the sidewall or sidewalls of aperture 56. For example, layer 61(shown in FIG. 4) of a material from which collar 60 is formed can beconformally deposited on dielectric layer 54 and the walls of aperture56. Conformal coverage yields a substantially vertical sidewall in thedielectric aperture. While not preferred, a partially conformal layer ofthe material can be deposited instead. A highly conformal process ispreferably employed to form layer 61. Portions of layer 61 on the bottomof aperture 56 and top of dielectric layer 54 are then removed,preferably by using an appropriate directional etch, such as reactiveion etching (RIE).

Conducting layer 62 is next deposited or otherwise formed to fillaperture 56 and extend over dielectric layer 54, as shown in brokenlines in FIG. 5. Conducting layer 62 may be deposited by any IC devicefabrication method yielding the desired characteristics. For example,conducting layer 62 may be deposited by a conformal or non-conformaldeposition process. An abrasive planarization process, such aschemical-mechanical planarization (CMP), is then used to remove portionsabove the horizontal plane of the upper surface of dielectric layer 54and leave conductive plug (in a via 56) or line (in a trench 56) 64 asillustrated in FIG. 6.

Similar to conducting layer 10, conducting layer 62 comprises anyconducting material used in IC devices. Preferably, conducting layer 62comprises aluminum, optionally containing other metals such as Si, W,Ti, and/or Cu. More preferably, conducting layer 62 is analuminum-copper alloy. Conducting layer 62 may also comprise coppermetal.

Dielectric layer 54 can then be optionally removed, thus forming theinterconnect structure represented in FIG. 7 a. Dielectric layer 54 canbe removed by any process which does not degrade any of metal layer 52,conducting layer 62, or collar 60. For example, when dielectric layer 54is silicon oxide, it may be removed by an HF wet etch solution or anoxide dry etch process. If desired, portions of metal layer 52 can thenbe removed, preferably by a directional etching process, to obtain theinterconnect structure shown in FIG. 7 b.

In an alternative method, upper metal layer 66 can be formed overconductive plug or line 64 as depicted in FIG. 8. Like metal layer 52,upper metal layer 66 may contain one or more individual metal layers.Preferably, a single metal layer is used as upper metal layer 66.Similar to metal layer 52, upper metal layer 66 may contain not onlymetals but their alloys and compounds. Preferably, upper metal layer 66comprises the same material as collar 60. More preferably, whenconductive plug 64 comprises Al, upper metal layer 66 comprises Ti.

Upper metal layer 66 can be formed over conductive plug 64 in thefollowing manner. Conducting layer 62 is deposited in aperture 56 andover dielectric layer 54 as described above with respect to FIG. 5.Prior to completely filling aperture 56, however, the deposition ofconducting layer 62 is halted as shown at 62 a in FIG. 5, leaving anupper portion of aperture 56 empty (i.e., a recess is left at the top ofaperture 56). Upper metal layer 66 is then deposited over conductinglayer 62, including the still-empty upper portion of aperture 56.Portions of conducting layer 62 and upper metal layer 66 above thehorizontal plane of dielectric layer 54 are then removed by aplanarization process, such as CMP, to form a completely enveloped, orclad, interconnect structure. If desired, portions of dielectric layer54 and metal layer 52 flanking the interconnect structure can be removedas described above to form the structure of FIG. 9.

In another process variant, after forming metal layer 52 on substrate 50and forming dielectric layer 54 with aperture 56 therethrough, but priorto forming collar 60, conductive plug or line 64 could be formed inaperture 56 as described above. Upper metal layer 66 could then bedeposited, as described above, over conductive plug or line 64 anddielectric layer 54 to obtain the structure illustrated in FIG. 10.Portions of upper metal layer 66 not overlying conductive plug or line64 could then be removed by a photolithographic pattern and etchprocess, followed by removing dielectric layer 54 by the methoddescribed above, to obtain the structure illustrated in FIG. 11. Asexplained above, the structure of FIG. 11 could then have a conformedmetal layer deposited and etched (similar to the deposition and etch ofsecond metal layer 14 above) to form a structure similar to thatdepicted in FIG. 3 a.

While the preferred embodiments of the present invention have beendescribed above, the invention defined by the appended claims is not tobe limited by particular details set forth in the above description, asmany apparent variations thereof are possible without departing from thespirit or scope thereof.

1. A method for making a metallization structure comprising: forming asubstrate comprising at least one metal layer on a surface thereof;forming a dielectric layer over the at least one metal layer; forming anaperture having at least one sidewall through the dielectric layer toexpose a surface of the at least one metal layer; forming a metal spacercompletely flanking the at least one sidewall of the aperture andcontacting the least one metal layer; and forming a conductive layer ina remaining portion of the aperture such that at least a bottom surfaceof the conductive layer contacts a portion of the at least one metallayer.
 2. The method of claim 1, further comprising forming thedielectric layer of silicon oxide.
 3. The method of claim 1, furthercomprising forming the at least one metal layer of Ti, Ta, W, Co or Moor alloys or compounds thereof, including TaN or TiN.
 4. The method ofclaim 3, wherein the at least one metal layer comprises a first metallayer, and further comprising forming a second metal layer between thefirst metal layer and the substrate, the second metal layer comprisingTiN, TiW, WN, or TaN.
 5. The method of claim 1, further comprisingforming the at least one metal layer of titanium or titanium nitride. 6.The method of claim 1, further comprising forming the at least one metallayer by vapor deposition.
 7. The method of claim 6, further comprisingforming the at least one metal layer by CVD, PVD or PECVD.
 8. The methodof claim 1, further comprising forming the conductive layer by vapordeposition.
 9. The method of claim 8, further comprising forming theconductive layer by CVD, PVD or PECVD.
 10. The method of claim 1,further comprising forming the at least one metal layer and the metalspacer of the same metal.
 11. The method of claim 1, further comprisingforming the metal spacer by vapor deposition and directional etching.12. The method of claim 1, further comprising forming the metal spacerof at least one layer of Ti, Ta, W, Co or Mo, or alloys or compoundsthereof, including TaN or TiN.
 13. The method of claim 1, furthercomprising forming the metal spacer of titanium or titanium nitride. 14.The method of claim 1, further comprising forming at least one uppermetal layer on the conductive layer.
 15. The method of claim 14, furthercomprising forming the at least one upper metal layer on the conductivelayer from Ti, Ta, W, Co or Mo or alloys or compounds thereof, includingTaN or TiN.
 16. The method of claim 14, further comprising forming theat least one upper metal layer as a plurality of upper metal layers. 17.The method of claim 14, further comprising forming the at least oneupper metal layer of titanium or titanium nitride.
 18. The method ofclaim 14, further comprising forming the at least one upper metal layerby vapor deposition.
 19. The method of claim 18, wherein the vapordeposition is effected by CVD, PVD or PECVD.
 20. The method of claim 1,further comprising removing the dielectric layer and portions of the atleast one metal layer not underlying the aperture.
 21. The method ofclaim 20, further comprising removing the dielectric layer by using ahydrofluoric acid wet etch solution or an oxide dry etch process. 22.The method of claim 20, further comprising removing the portions of theat least one metal layer by directional etching.
 23. A method for makinga metallization structure comprising: forming a substrate comprising atleast one metal layer on a surface thereof; forming a dielectric layerover the at least one metal layer; forming an aperture through thedielectric layer to expose a surface of the at least one metal layer;forming a conducting layer in the aperture such that at least a bottomsurface of the conducting layer contacts a portion of the at least onemetal layer; forming at least one upper metal layer overlying thedielectric layer and the conducting layer in the aperture; removingportions of the at least one upper metal layer overlying the dielectriclayer, removing the dielectric layer, and removing portions of the atleast one metal layer surrounding the conducting layer to form amultilayer metal structure having at least one sidewall; and forming ametal spacer flanking the at least one sidewall of the multilayer metalstructure.
 24. The method of claim 23, further comprising forming thedielectric layer of silicon oxide.
 25. The method of claim 23, furthercomprising forming the at least one metal layer of Ti, Ta, W, Co or Moor alloys or compounds thereof, including TaN or TiN.
 26. The method ofclaim 25, wherein the at least one metal layer comprises a first metallayer, and further including forming a second metal layer between thefirst metal layer and the substrate, the second metal layer comprisingTiN, TiW, WN, or TaN.
 27. The method of claim 23, further comprisingforming the at least one metal layer of titanium or titanium nitride.28. The method of claim 23, further comprising forming the at least onemetal layer by vapor deposition.
 29. The method of claim 28, furthercomprising forming the at least one metal layer by CVD, PVD or PECVD.30. The method of claim 23, further comprising forming the conductinglayer by vapor deposition.
 31. The method of claim 30, furthercomprising forming the conducting layer by CVD, PVD or PECVD.
 32. Themethod of claim 23, further comprising forming the at least one metallayer and the metal spacer of the same metal.
 33. The method of claim23, further comprising forming the metal spacer by vapor deposition of ametal layer over the multilayer metal structure and directional etchingof the vapor-deposited metal layer.
 34. The method of claim 23, furthercomprising forming the metal spacer of at least one layer of Ti, Ta, W,Co or Mo, or alloys thereof or compounds thereof, including TaN or TiN.35. The method of claim 23, further comprising forming the metal spacerof titanium or titanium nitride.
 36. The method of claim 23, furthercomprising forming the at least one upper metal layer overlying thedielectric layer from Ti, Ta, W, Co or Mo or an alloy or a compound ofany thereof, including TaN or TiN.
 37. The method of claim 36, furthercomprising forming the at least one upper metal layer as a plurality ofupper metal layers.
 38. The method of claim 23, further comprisingforming the at least one upper metal layer of titanium or titaniumnitride.
 39. The method of claim 23, further comprising forming the atleast one upper metal layer by vapor deposition.
 40. The method of claim39, wherein the vapor deposition is effected by CVD, PVD or PECVD. 41.The method of claim 23, further comprising removing the dielectric layerby using a hydrofluoric acid wet etch solution or an oxide dry etchprocess.
 42. The method of claim 23, further comprising removing theportions of the at least one metal layer by directional etching.
 43. Themethod of claim 23, further comprising forming the conducting layer fromat least one of aluminum and copper.
 44. The method of claim 23, furthercomprising forming the at least one metal layer, metal spacer, and atleast one upper metal layer of the same metal.
 45. The method of claim44, wherein the same metal is Ti.